Multithreaded programs are notoriously prone to unintended interference between concurrent threads. To address this problem, we argue that yield annotations in the source code should document all thread interference, and we present a type system for verifying the absence of undocumented interference. Well-typed programs behave as if context switches occur only at yield annotations. Thus, they can be understood using intuitive sequential reasoning, except where yield annotations remind the programmer to account for thread interference.

Experimental results show that our type system for yield annotations is more precise than prior techniques based on method-level atomicity, reducing the number of interference points by an order of magnitude. The type system is also more precise than prior methods targeting race freedom. In addition, yield annotations highlight all known concurrency defects in our benchmark suite.

This is joint work with Cormac Flanagan, Jaeheon Yi, Caitlin Sadowski at UC Santa Cruz.

Bio:

Stephen Freund is an Associate Professor and Chair of the Computer Science Department at Williams College. His current research focuses on light-weight analyses to identify defects in concurrent software, such as race conditions, atomicity errors, and specification violations. Prior to joining Williams in 2002, Steve worked at the Compaq Systems Research Center on various programmer productivity tools. He received his PhD from Stanford University in 2000.

Over the last several years, JavaScript malware has emerged as one of the most popular ways to deliver drive-by attacks to unsuspecting users through the browser. This talk covers recent Microsoft Research experiences with finding malware on the web. It highlights two tools: Nozzle and Zozzle. Nozzle is a runtime malware detector that focuses on finding heap spraying attacks. Zozzle is a mostly static detector that finds heap sprays and other types of JavaScript malware. Both are extremely precise: Nozzle false positive rate is close to one in a billion; Zozzle's is about one in a million.

Both are deployed by Bing and are used daily to find thousands of malicious web sites. This talk will focus on interesting interplay between static and runtime analysis and cover what it takes to migrate research ideas into real-world products.

Nozzle is deployed at Bing and has been finding thousands of malware sites daily for months now. Initial estimates show that with Zozzle, the team can go even further in detecting malicious sites. The focus of Zozzle is on providing a very fast and accurate scanner for detecting malware in JavaScript code. Zozzle is able to process a megabyte of code in a second and finds malware with a false positive rate of one in a million JavaScript documents.

Bio:

Ben Livshits is a researcher at Microsoft Research in Redmond, WA and an affiliate professor at the University of Washington. Originally from St. Petersburg, Russia, he received a bachelor's degree in Computer Science and Math from Cornell University in 1999, and his M.S. and Ph.D. in Computer Science from Stanford University in 2002 and 2006, respectively. Dr. Livshits' research interests include application of sophisticated static and dynamic analysis techniques to finding errors in programs.

Ben has published papers at PLDI, Oakland Security, Usenix Security, CCS, SOSP, ICSE, FSE, and many other venues. He is known for his work in software reliability and especially tools to improve software security, with a primary focus on approaches to finding buffer overruns in C programs and a variety of security vulnerabilities (cross-site scripting, SQL injections, etc.) in Web-based applications. He is the author of several dozen academic papers and patents. Lately he has been focusing on how Web 2.0 application and browser reliability, performance, and security can be improved through a combination of static and runtime techniques. Ben generally does not speak of himself in the third person.

Debugging run-time errors remains one of the most time-consuming, and sometimes frustrating, efforts in developing and maintaining programs. A run-time error is uncovered, and the programmer then begins multiple iterations within a debugger in order to build up a hypothesis about the original program fault that caused the error. Examples of run-time errors include segmentation fault, assertion failure, infinite loop, deadlock, livelock, and missing synchronization locks.

This talk describes a debugging approach based on a reversible debugger, sometimes known as a time-traveling debugger. This is a more natural approach, since it allows a programmer during a single program run to work backwards from run-time error to earlier fault, and still earlier to the original causal fault. A new tool, reverse expression watchpoints, allows one to begin with a program error and an expression that has an incorrect value, and automatically bring the programmer backwards in time to a point at which the expression first took on an incorrect value. This tool is part of a long-range project in which a series of such tools is planned --- each tool customized for a different class of run-time errors.

The long-term goals described here are motivated by an analogy between syntax errors and run-time errors:

1. Currently, syntax errors are easily diagnosed by compilers that bring the programmer directly to the line number, within a textual program, that led to the bad syntax.
2. In the future, run-time errors will be easily diagnosed by a new class of reversible debugger tools that bring the programmer directly to the point in time, within a familiar debugging environment, that led to the later run-time error.

The reversible debugger is itself based on a fast, transparent checkpointing package for Linux: DMTCP (Distributed MultiThreaded CheckPointing). DMTCP can checkpoint such varied programs as Matlab, OpenMPI, MySQL, Python, Perl, GNU screen, Vim, Emacs, and most user-developed programs, regardless of the implementation language. No kernel modification or other root privilege is needed. Of particular interest for this talk is the ability of a customized version of DMTCP to checkpoint an entire gdb session. The reversible debugger also supports weak determinism for purposes of debugging multi-threaded programs. The current implementation has been demonstrated robust enough to run such large, real-world programs as MySQL and Firefox.

Bio:

Gene Cooperman received his Ph.D. from Brown University in 1978. He spent two years as a post-doc, followed by six years at GTE Laboratories. He has been a professor at Northeastern University since 1986, and a full professor since 1992. His interests lie in high performance computation and symbolic algebra. The first interest is currently focussed on DMTCP, a robust transparent checkpointing package that does not require any modifications to the application or kernel/run-time library. A combination of the two interests has led to his joint work on the Roomy language extension to translate traditional RAM-intensive computations into scalable computations based on parallel disks. A variation for remote RAM and supercomputing is being developed for the Madness software at Oak Ridge National Laboratory. He also has a decade-long relationship with CERN, where he supports semi-automatic thread parallelization of task-oriented software, such as Geant4 at CERN. He leads the High Performance Computing Laboratory at Northeastern University, where he currently advises four PhD students. He has over 80 refereed publications.

Over the past few years parallel dataflow graph frameworks (such as MapReduce, Hadoop, Dryad) have enabled data intensive computing on clusters built from commodity hardware. A key component in a parallel dataflow graph computation is the intermediate data that flows between various computation stages. This data is generated during the computation and, in general, has to be moved across machines in the cluster involving network I/O as well as disk I/O. At large volumes (viz., 10's to 100's of terabytes of data), unless careful attention is paid to disk overheads involved in dealing with intermediate data, cluster throughput will degrade.

In this talk, we describe a new approach to handling intermediate data at scale. We find that managing large volumes of intermediate data requires novel batching mechanisms to reduce disk subsystem overheads. Our approach is to build filesystem support specifically for storing intermediate data. We design an atomic record append primitive that enables concurrent writers to append to a file in a lock-free manner: multiple writers append to a block and multiple blocks of a file can be appended to concurrently. We denote files constructed via atomic append I-files. I-file blocks are written to sequentially and are read back mostly sequentially. We have developed an implementation of I-files and used it as the foundation for Sailfish, a MapReduce framework we built by modifying Hadoop. We have also used Sailfish to run unmodified Hadoop MapReduce jobs that process production datasets. Our results show that for transporting intermediate data at scale, Sailfish can outperform Hadoop by at least a factor of 2.

Bio:

Sriram is a member of the Cloud Sciences group at Yahoo! Labs. His interests are in building distributed storage systems that enable high performance compute services for processing massive datasets. At Yahoo!, Sriram leads the Sailfish project whose goal is to enable large-scale analytics on big data. Prior to Yahoo!, Sriram led the design and implementation of KFS (Kosmos Filesystem), an open-source filesystem project. KFS is deployed in production settings where it is used to manage multiple-PB's of storage.

As hardware and software continues to evolve into increasingly complex systems, our ability to understand their behavior and measure their performance is increasingly difficult.

Nevertheless, many areas of computer science use experiments to identify performance bottlenecks and to evaluate innovations. In the last few years, researchers have identified some disturbing flaws in the way that experiments are performed in computer science.

This talk presents two of these flaws.

First, changing a seemingly innocuous aspect of an experimental setup can result in a systems researcher drawing wrong conclusions from an experiment. What appears to be an innocuous aspect in the experimental setup may in fact introduce a significant bias in an evaluation of native (C and C++) applications.

Second, performance analysts profile their programs to find methods that are worth optimizing: the “hot” methods; however, four commonly used Java profilers (xprof , hprof , jprofile, and yourkit) often disagree on the identity of the hot methods. This talk demonstrates that these profilers all violate a fundamental requirement for sampling based profilers: to be correct, a sampling-based profiler must collect samples randomly.

Unfortunately, the flaws discussed above are not the full extent of the problem. If computer science is to be taken seriously as a scientific discipline, we as a community need to do a better job designing experiments and evaluating their results.

I will discuss some current efforts being made by the community to improve experimental evaluation in computer science.

Bio:

Peter F. Sweeney is a Research Staff Member in the Program Technology Department at the IBM T.J. Watson Research Center in Hawthorne, New York. His current research interests are performance analysis and tuning of computer systems with a focus on automation. In the past, he has focused on object-oriented optimization. Peter received a Master's degree in Computer Science from Columbia University SEAS and he joined IBM Research in 1985. Peter is a senior member of ACM and a co-author of the paper "Adaptive optimization in the Jalapeno JVM", which received the 2010 ACM SIGPLAN most influential OOPSLA 2000 paper award.

Challenges in digital services delivery: the cloud vs. the crowd (Diot)

The universal answer to home service delivery these days seems to be "the cloud", even though nobody really agrees on what "cloud services" means. In order to bring some transparency to the Cloud, we identify what are the challenges in digital home services delivery, discuss the strengths and limitations of a pure cloud approach, and finally propose an hybrid solution relying both on data centers and home devices to better serve home users. We discuss the research and technology challenges that have to be solved to deploy this digital service delivery architecture.

Performance of Networked Applications: The Challenges in Capturing the User’s Perception (Teixeira)

There is much interest recently in doing automated performance diagnosis on user laptops or desktops. One interesting aspect of performance diagnosis that has received little attention is the user perspective on performance. To conduct research on both end-host performance diagnosis and user perception of network and application performance, we designed an end-host data collection tool, called HostView. HostView not only collects network, application and machine level data, but also gathers feedback directly from users. User feedback is obtained via two mechanisms, a system-triggered questionnaire and a user-triggered feedback form, that for example asks users to rate the performance of their network and applications. This talk will describe our experience with the first deployment of HostView. Using data from 40 users, we illustrate the diversity of our users, articulate the challenges in this line of research, and report on initial findings in correlating user data to system-level data. This is joint work with Diana Joumblatt, Jaideep Chandrashekar, and Nina Taft.

 

A multi-domain cloud combines virtual infrastructure from multiple providers to create a powerful platform for networked services, computation, and experimental systems research. NSF's GENI initiative (Global Environment for Network Innovation) is a key example of a multi-domain infrastructure-as-a-service (IaaS) system: it generalizes IaaS cloud computing to incorporate diverse virtual infrastructures, noncommercial providers, configurable network connectivity, and software-defined networking.

One lesson we can draw from the GENI experience is that many of the technical challenges for the GENI control framework ultimately reduce to issues of trust and authorization. In this talk, I will outline an emerging architecture based on declarative policy for federation trust structure and authorization for access to cloud resources. The approach uses libabac from ISI, an open-source implementation of an authorization logic called Attribute-Based Access Control (ABAC). I also address the question of how to incorporate software identities as subjects in the authorization framework. How do we know if we can trust applications and services running in the cloud? I discuss preliminary research on Trusted Platform Cloud, which uses attestations by cloud providers to infer trust for autonomous software instances.

Bio:

Jeff Chase is a Professor of Computer Science at Duke University and a Visiting Scientist at the Renaissance Computing Institute (RENCI). He has spent much of the last four years working on the GENI control framework as a Control Framework Working Group chair and as leader of the Open Resource Control Architecture (ORCA) project. He is co-chair of the 2011 ACM Symposium on Cloud Computing (SOCC).

This presentation will describe four ongoing projects that are advised by my computer-architecture colleague Luis Ceze and that I am co-advising or contributing to. For each, I will point out what aprogramming-languages perspective has to offer and why it is useful to have students who can nimbly cross or blur the hardware/software divide. The projects — deterministic execution of multithreaded programs, code-centric specification of shared memory, language support for approximate low-power computing, and run-time errors for data races — address the key technology trends of ubiquitous parallelism and energy as a first-order concern.

Bio:

Dan Grossman is an Associate Professor in the Department of Computer Science & Engineering at the University of Washington where he has been a faculty member since 2003. Grossman completed his Ph.D. at Cornell University and his undergraduate studies at Rice University. His research interests lie in the area of programming languages, ranging from theory to design to implementation, with a focus on improving software quality. In recent years he has focused on better techniques for expressing multithreaded programs, particularly using languages with well-defined support for transactional memory. In prior work, he focused on type-safe systems programming using the Cyclone language, which he developed with colleagues.

Grossman has served on over fifteen conference and workshop program committees in addition to co-chairing the 2007 ACM SIGPLAN-SIGSOFT PASTE workshop and the 2009 ACM SIGPLAN TRANSACT workshop. He currently serves on the ACM SIGPLAN Executive Committee and the ACM Education Council. He is the recipient of an NSF Career Award and two "Teacher of the Year" Awards voted on by his department's undergraduates.

In his spare time, Dan can be found playing ice hockey (poorly), bicycling, hiking, or enjoying good food, beer, and theatre. Dan has never had a cavity.

Many multithreaded concurrency platforms that use a work-stealing runtime system incorporate a "cactus stack," wherein the stack variables that can be accessed by functions properly respect the functions' calling ancestry, even when many of the functions operate in parallel. Unfortunately, such existing concurrency platforms fail to satisfy at least one of the following three desiderata:

• full interoperability with legacy or third-party serial binaries that have been compiled to use an ordinary linear stack,
• a scheduler that provides near-perfect linear speedup on applications with sufficient parallelism, and
• bounded and efficient use of memory for the cactus stack.

We have addressed this cactus-stack problem by modifying the Linux operating system kernel to provide support for thread-local memory mapping (TLMM). We have used TLMM to reimplement the cactus stack in the open-source Cilk-5 runtime system. Our prototype Cilk-M runtime system removes the linguistic distinction imposed by Cilk-5 between serial code and parallel code, erases Cilk-5's limitation that serial code cannot call parallel code, and provides full compatibility with existing serial calling conventions. The Cilk-M runtime system provides strong guarantees on scheduler performance and stack space. Benchmark results indicate that the performance of the prototype Cilk-M is comparable to the Cilk-5 system, and the consumption of stack space is modest.

Bio:

I-Ting Angelina Lee is a Ph.D. student in computer science at the Massachusetts Institute of Technology, working with Prof. Charles E. Leiserson. Her primary research interest is in the design and implementation of programming models, languages, and managed runtime environments to support multithreaded software, with an emphasis on efficient implementations with theoretical foundations. She designed and implemented JCilk, a Java-based Cilk that has exception-handling semantics which integrate synergistically with the multithreading provided by Cilk's fork-join primitives. She developed the "ownership-aware" transactional-memory methodology for handling nested transactions that, unlike previous proposals, admits more concurrency and provides provable safety guarantees. Her current focus is on memory abstractions for parallel computing, and she is actively developing Cilk-M, a concurrency platform that uses thread-local memory mapping to support cactus stacks and hyperobjects. She received her Bachelor of Science in Computer Science from UC San Diego in 2003, where she worked on the Simultaneous Multithreading Simulator for DEC Alpha under the supervision of Prof. Dean Tullsen.

Hardware is the root of trust in computer systems, because all software runs on it. Economic, technological, and social factors make it increasingly difficult to build trustworthy hardware. Use of third-party intellectual property components, the global scope of the chip design process, increased design complexity and integration, growing design teams with relatively small numbers of designers responsible for each sub-component all conspire to make hardware more susceptible to malicious design and less trustworthy than in the past. Untrustworthy hardware is already a concern for military and public safety equipment as evidenced by the recent discovery of hardware "kill switches" in mission critical systems. In this talk I will provide a complete taxonomy of digital hardware attacks and use this taxonomy to derive a range of possible solutions to make hardware trustworthy.

Bio:

Simha Sethumadhavan is an Assistant Professor of Computer Science at Columbia University. He directs the computer architecture and security technologies lab (CASTL) at Columbia University. Prof. Sethumadhavan’s research interests are in hardware security, hardware support for security and privacy, energy-efficient computing and systems research tools. He has been recognized with teaching and research awards. He obtained his PhD from UT Austin in 2007.

Modern microprocessors achieve high performance through aggressive speculation. However, large amounts of energy and potential performance are lost by speculating fruitlessly. The two most important speculation techniques are caches and speculative execution.

Caches hold a subset of the blocks from the high-latency main memory, speculating that quick access to these blocks will benefit the program. Unfortunately, most blocks in the last-level cache will not be referenced again before they are removed from the cache. These dead blocks waste time and energy as they reduce the effective capacity of the cache.

Speculative execution mitigates pipeline control hazards by predicting the outcome of branches, allowing subsequent instructions to be fetched and executed down the predicted path. Many instructions will be wrongly executed before an incorrect prediction is discovered, again wasting time and energy.

This talk discusses novel techniques for reclaiming lost performance and energy through reducing speculation wasted by caches and speculative execution. The talk will also discuss ongoing projects and future research directions.

Bio: Daniel A. Jimenez is an Associate Professor in the Department of Computer Science at The University of Texas at San Antonio. He is currently on leave at the Barcelona Supercomputing Center. His research focuses on microarchitecture and low-level compiler optimizations. From 2002 through 2007, Daniel was an Assistant Professor in the Department of Computer Science at Rutgers. In 2005 Daniel took sabbatical leave at the Technical University of Catalonia (UPC) in Barcelona, Catalonia, Spain. In 2008 he was promoted to Associate Professor with tenure at Rutgers. Daniel earned his B.S. (1992) and M.S. (1994) in Computer Science at The University of Texas at San Antonio and his Ph.D. (2002) in Computer Sciences at The University of Texas at Austin. He is an NSF CAREER award recipient, an ACM Senior Member, and General Chair of the 2011 HPCA conference.

We have always known that a given problem can be solved using multiple algorithms; and the best solution for each input or architecture may require a different algorithm. However, currently there is no simple way for the programmer to express or the compiler to take advantage of all the available algorithmic choices for a problem. In this talk I will present PetaBricks, a new implicitly parallel language and compiler where having multiple implementations of multiple algorithms to solve a problem is the natural way of programming. The PetaBricks compiler autotunes programs by making the best fine-grained algorithmic choices. Choices also include different automatic parallelization techniques, data distributions, algorithmic parameters, transformations, and blocking.

Bio: Saman P. Amarasinghe is a Professor in the Department of Electrical Engineering and Computer Science at Massachusetts Institute of Technology and a member of the Computer Science and Artificial intelligence Laboratory (CSAIL). Currently he leads the Commit compiler group. His research interests are discovering novel approaches to improve the performance of modern computer systems and make them more secure without unduly increasing the complexity faced by either the end users, application developers, compiler writers, or computer architects. Saman received his BS in Electrical Engineering and Computer Science from Cornell University in 1988, and his MSEE and Ph.D from Stanford University in 1990 and 1997, respectively.

In this talk I will introduce SciDB, a new open-source and massively parallel platform for array data storage, processing, and analysis. I will review a number of scientific use-cases and describe how these use-cases have determined the features and functionality of the system. I will introduce SciDB's data model, and will describe some of the key architectural features of the system including columnar storage, parallel user-defined functions, and overlapping array partitioning. Finally, I will introduce SSDB, a new benchmark for scientific data management systems, and will explain why SciDB is two orders of magnitude faster than traditional database systems on common large-scale array processing tasks.

Bio: Philippe Cudré-Mauroux is a postdoctoral associate working in the Database Systems group at MIT. He received his Ph.D. from the Swiss Federal Institute of Technology EPFL, where he won the Doctorate Award and the EPFL Press Mention in 2007. Before joining MIT, he worked on distributed information management systems for HP, IBM T.J. Watson Research, and Microsoft Research Asia. His research interests are in large-scale distributed infrastructures for non-relational data such as spatiotemporal, scientific, or Semantic Web data.

Loss avoidance has long been central to the Internet architecture. Ordinarily, dropped packets represent wasted resources. In this talk, I'll posit that the benefits of a network architecture that embraces---rather than avoids---widespread packet loss outweigh the potential loss in efficiency. I'll propose an alternative approach to Internet congestion control called decongestion control. In a departure from traditional approaches, in this approach, end hosts strive to transmit packets faster than the network can deliver them, leveraging end-to-end erasure coding and in-network fairness enforcement. I'll argue that such an approach may improve stability, robustness, and tolerance for misbehavior. While a number of important design issues remain open, I'll show that our approach not only avoids congestion collapse, but delivers high steady-state goodput for a variety of traffic demands in different backbone topologies.

Bio: Barath Raghavan is a visiting assistant professor of Computer Science at Williams College for 2009-2010. He received his Ph.D. in Computer Science from UC San Diego in 2009 and his B.S. in EECS from UC Berkeley in 2002. He received the 2007 ACM SIGCOMM best paper award and a 2004 NSF graduate research fellowship. Barath's primary research interests include networks, security, distributed systems, and cryptography.

Failure mode and effects analysis (FMEA) is an established technique to reason about possible system hazards that result from system or system component failures. Traditionally, FMEA does not take the probabilities with which these failures may occur into account. Recently, this shortcoming was addressed by integrating stochastic model checking techniques into the FMEA process. I will illustrate how to apply this extended technique, that we refer to as probabilistic FMEA (pFMEA), to the design of an airbag electronic control unit under development of our industrial partner TRW Automotive GmbH. Since FMEA aims at improving safety-critical system designs, it was essential to adequately represent the causal factors that lead to failures. To this end we use a counterexample visualization add-on to the stochastic model checker PRISM that we have recently developed.

HTTP, the foundation protocol of the Web as it exists today, was finalized in 1999. Back then, the Web was still mostly a collection of static pages linked together, and those pages included very few resources. Today, the Web is drastically different - pages are overloaded with various resources and bits of logic tying it all together. Yet these rich pages are delivered over the wire essentially the same way as they were over a decade ago, resulting in poor user experience (try loading any major news website - it's slow).

SPDY is an attempt to rethink how we deliver the content on the Web, optimizing for a better, faster user experience. SPDY is a new application-layer protocol for delivering web pages and web apps that solves some of the performance problems associated with HTTP. It is backwards-compatible with existing web content (both static and dynamic), and significantly lowers page load times without requiring any changes to said content.

Bio:

Vitaliy Lvin received a B.S. in computer science from UMass Amherst in 2005, followed by an M.S. in 2007. Since joining Google in 2007, he has been working on various pieces of front-end serving infrastructure. Recently, he has been heavily involved in the server-side implementation of SPDY at Google, as well in the design of the protocol itself.

Modern computer system designers must consider many more factors than raw performance of individual applications. Thermal output, power consumption, reliability, heterogeneity, and dynamic resource contention have become first-order concerns. Yet many of these issues are transient in nature, are difficult to predict, and are expensive to completely avoid. These observations point toward the potential benefits of adaptive systems that detect and react to changing conditions as they arise.

Historically, research efforts in optimizing computer systems have targeted a single logical layer in the system stack, whether it has been optimization of the hardware (microarchitectural or circuit-level techniques), the middleware (operating systems and virtual machines), or the software (static and dynamic compilation). However, a true adaptive system requires coordination of all layers to be effective. While hardware is ideal for detecting thermal emergencies, for instance, the middleware has a global view of the runtime environment, including resource contention and observed process heterogeneity, and the software has a global view of the opportunities for permanent code-based solutions that leverage dynamic information.

In this talk, I will make a case for dynamic adaptation as a solution for several modern architectural and system challenges, such as voltage noise, heterogeneous scheduling, and thermal output. I will discuss our research efforts in integrating the strengths of each design layer to provide cohesive, symbiotic solutions to these challenges. Finally, I will highlight the numerous benefits of runtime adaptation moving forward.

Bio:

Kim Hazelwood is an Assistant Professor of Computer Science at the University of Virginia and a faculty consultant for Intel. She works at the boundary between hardware and software, with research efforts focusing on computer architecture, run-time optimizations, and the implementation and applications of virtual execution environments. She received a Ph.D. degree from Harvard University in 2004. Since then, she has become widely known for her active contributions to the Pin dynamic instrumentation system, which allows users to easily inject arbitrary code into existing program binaries at run time (www.pintool.org). Pin is widely used throughout industry and academia to investigate new approaches to program introspection, optimization, security, and architectural design. It has been downloaded over 35,000 times and cited in over 500 publications since it was released in July 2004. Kim has published over 35 peer-reviewed articles related computer architecture and virtualization. She has served on over a dozen program committees, including ISCA, PLDI, MICRO, and PACT, and is the program chair of CGO 2010. Kim is the recipient of numerous awards, including the FEST Distinguished Young Investigator Award for Excellence in Science and Technology, an NSF CAREER Award, a Woodrow Wilson Career Enhancement Fellowship, the Anita Borg Early Career Award, and research awards from Microsoft, Google, NSF, and the SRC. Her research has been featured in Computer World, ZDNet, EE Times, and Slashdot.

Stream processing applications such as algorithmic trading, traffic management, and telecom services are ubiquitous and essential to business and entertainment. Stream processing makes it easy to exploit pipeline, task, and data parallelism, but programming languages for stream processing must address several challenges, including performance, safety, generality, and portability. This talk surveys diverse stream processing languages, and formulates a core calculus, Brooklet, that helps explain and compare their operational semantics. Next, this talk describes solutions to various programming language challenges in the context of SPL, the language for System S, IBM's distributed stream processing middleware. Stream processing is both commercially profitable and academically challenging, making it fertile ground for relevant innovation.

Bio:

Martin Hirzel is a researcher at IBM's T.J. Watson Research Center in New York, where he works on programming languages and compilers. He has also taught classes as an adjunct professor at NYU. Martin received his Ph.D. from the University of Colorado at Boulder in 2004 under the supervision of Amer Diwan.

Reducing energy consumption, improving performance, and tolerating failures are important goals in modern computing systems. We present two techniques for satisfying these goals. The first technique, loop perforation, finds the most time-consuming loops, then transforms the loops to execute fewer iterations. Our results show that this technique can reduce the computational resources required to execute the application by a factor of two to three (enabling corresponding improvements in energy consumption, performance, and fault tolerance) while delivering good quality of service. The second technique, goal-directed parallelization, executes the most time-consuming loops in parallel, then (guided by memory profiling information) adds synchronization and replication as necessary to eliminate bottlenecks and enable the application to produce accurate output. Our results show that this approach makes it possible to effectively parallelize challenging applications without the use of complex static analysis.

Because traditional program transformations operate in the absence of any specification of acceptable program behavior, the transformed program must produce the identical result as the original program. In contrast, the two techniques presented in this talk exploit the availability of quality of service specifications to apply much more aggressive transformations that may change the result that the program produces (as long as the result satisfies the specified quality of service requirements). The success of these two techniques demonstrates the advantages of this approach.

Bio:

Martin Rinard is a Professor in the MIT Department of Electrical Engineering and Computer Science and a member of the MIT Computer Science and Artificial Intelligence Laboratory. His research interests include parallel and distributed computing, programming languages, program analysis, program verification, software engineering, and computer systems. Much of his current research focuses on techniques that enable software systems to survive otherwise fatal errors or anomalies. Results in this area include acceptability-oriented computing (a framework for ensuring that software systems satisfy basic acceptability properties), failure-oblivious computing (a technique for enabling programs to execute successfully through otherwise fatal memory addressing errors), and a technique for providing probabilistic bounds on the accuracy of program outputs in the presence of failures.

The traditional process of performance diagnosis and tuning will become harder to manage as the factors of scale, software complexity, hardware integration, and heterogeneity continue to increase. While interactions among these factors create the need to observe application performance across the whole system hierarchy, it is the model-oriented knowledge of the computational semantics of the application and of performance expectations with respect to peta/exascale systems architectures and capabilities that ultimately must be incorporated into performance tools to better focus and automate performance problem identification and guide tuning decisions. In addition, by supporting a higher-level (model-oriented) abstraction for performance investigation, application developers can be more directly involved in the performance engineering process. However, it is also necessary to continue to provide measurement features that expose the events necessary for model-oriented performance views. Results from recent work with Charm++ and GPUs will be discussed.

Bio:

Dr. Allen D. Mal

---

Department of Computer Science - 140 Governors Drive - Amherst, MA 01003
Copyright © 2006-11 Emery Berger, University of Massachusetts, Amherst